চূড়ান্ত প্রকল্প — একটি সিম্পল CPU সিমুলেটর বানানো

PC   ইনস্ট্রাকশন                 মন্তব্য
--   ------------------------    -----------------------------
 0   ADDI  r1, r0, 0             i = 0
 1   ADDI  r2, r0, 0             sum = 0
 2   ADDI  r3, r0, 5             limit = 5
 3   ADDI  r4, r0, 1             const_one = 1
 4   ADD   r1, r1, r4      <-- LOOP: i = i + 1
 5   ADD   r2, r2, r1             sum = sum + i
 6   BEQ   r1, r3, 1              i == limit হলে PC=8 (এক্সিটে যাও)
 7   BEQ   r0, r0, -4             নাহলে PC=4 (LOOP-এ ফিরে যাও, অ্যানকন্ডিশনাল জাম্প)
 8   STORE r2, 0(r0)              mem[0] = sum
 9   LOAD  r5, 0(r0)              r5 = mem[0]  (যাচাইয়ের জন্য আবার লোড)
10   HALT

class DirectMappedCache:
    """M8/L38 -- ডেটা মেমরির সামনে বসানো ডিরেক্ট-ম্যাপড ক্যাশ, হিট/মিস ট্র্যাক করে"""
    def __init__(self, num_lines=4):
        self.num_lines = num_lines
        self.lines = [{"valid": False, "tag": None, "data": 0} for _ in range(num_lines)]
        self.hits = 0
        self.misses = 0

    def _index_tag(self, address):
        return address % self.num_lines, address // self.num_lines

    def read(self, address, data_memory):
        index, tag = self._index_tag(address)
        line = self.lines[index]
        if line["valid"] and line["tag"] == tag:
            self.hits += 1
            return line["data"], "HIT"
        self.misses += 1
        value = data_memory.get(address, 0)
        line.update(valid=True, tag=tag, data=value)
        return value, "MISS"

    def write(self, address, value, data_memory):
        index, tag = self._index_tag(address)
        line = self.lines[index]
        status = "HIT" if (line["valid"] and line["tag"] == tag) else "MISS"
        if status == "HIT":
            self.hits += 1
        else:
            self.misses += 1
        line.update(valid=True, tag=tag, data=value)   # write-through: ক্যাশ + মেমরি দুটোই আপডেট
        data_memory[address] = value
        return status


class ALU:
    """M2/L09 + M4/L19 -- অ্যাডার/সাবট্রাক্টর-ভিত্তিক ALU, তুলনাসহ"""
    @staticmethod
    def execute(op, a, b):
        if op == "ADD":
            result = a + b
        elif op == "SUB":
            result = a - b
        elif op == "CMP":
            result = a - b
        else:
            raise ValueError(f"অজানা ALU অপারেশন: {op}")
        flags = {"zero": result == 0, "negative": result < 0}
        return result, flags


class RegisterFile:
    """M5/L26 -- সাধারণ-উদ্দেশ্য রেজিস্টার, r0 সবসময় ০, প্লাস PC/IR/flags"""
    def __init__(self, n=8):
        self.regs = [0] * n
        self.pc = 0
        self.ir = None
        self.flags = {"zero": False, "negative": False}

    def read(self, i):
        return 0 if i == 0 else self.regs[i]

    def write(self, i, value):
        if i != 0:
            self.regs[i] = value


class SimpleCPU:
    """M6/L31 -- মাল্টি-সাইকেল-স্টাইল ফেচ-ডিকোড-এক্সিকিউট-মেমরি-রাইটব্যাক কন্ট্রোল লুপ"""

    STAGE_CYCLES = {
        "ADD":   ["FETCH", "DECODE", "EXECUTE", "WRITEBACK"],
        "SUB":   ["FETCH", "DECODE", "EXECUTE", "WRITEBACK"],
        "ADDI":  ["FETCH", "DECODE", "EXECUTE", "WRITEBACK"],
        "LOAD":  ["FETCH", "DECODE", "EXECUTE", "MEMORY", "WRITEBACK"],
        "STORE": ["FETCH", "DECODE", "EXECUTE", "MEMORY"],
        "BEQ":   ["FETCH", "DECODE", "EXECUTE"],
        "HALT":  ["FETCH", "DECODE"],
    }

    def __init__(self, instruction_memory, cache_lines=4):
        self.imem = instruction_memory
        self.dmem = {}
        self.cache = DirectMappedCache(num_lines=cache_lines)
        self.rf = RegisterFile()
        self.alu = ALU()
        self.total_cycles = 0
        self.instructions_executed = 0
        self.trace = []
        self.halted = False

    def step(self):
        if self.halted:
            return False
        pc_before = self.rf.pc
        instr = self.imem[pc_before]
        op = instr["op"]
        stages = self.STAGE_CYCLES[op]
        rec = {"pc": pc_before, "instr": instr, "stages": ["FETCH", "DECODE"], "mem_status": None}

        self.rf.ir = instr                 # FETCH: ইনস্ট্রাকশন রেজিস্টারে লোড
        pc_next = pc_before + 1

        if op == "HALT":                   # DECODE-এই থেমে যায়
            self.halted = True
            self.total_cycles += len(stages)
            self.instructions_executed += 1
            self.trace.append(rec)
            return False

        rec["stages"].append("EXECUTE")
        result, branch_taken = None, False
        if op in ("ADD", "SUB"):
            a, b = self.rf.read(instr["rs1"]), self.rf.read(instr["rs2"])
            result, self.rf.flags = self.alu.execute(op, a, b)
        elif op == "ADDI":
            a = self.rf.read(instr["rs1"])
            result, self.rf.flags = self.alu.execute("ADD", a, instr["imm"])
        elif op in ("LOAD", "STORE"):
            rec["addr"] = self.rf.read(instr["rs1"]) + instr["offset"]
        elif op == "BEQ":
            a, b = self.rf.read(instr["rs1"]), self.rf.read(instr["rs2"])
            _, cmp_flags = self.alu.execute("CMP", a, b)
            branch_taken = cmp_flags["zero"]
            if branch_taken:
                pc_next = pc_before + 1 + instr["offset"]

        if "MEMORY" in stages:
            rec["stages"].append("MEMORY")
            if op == "LOAD":
                result, rec["mem_status"] = self.cache.read(rec["addr"], self.dmem)
            elif op == "STORE":
                rec["mem_status"] = self.cache.write(rec["addr"], self.rf.read(instr["rs2"]), self.dmem)

        if "WRITEBACK" in stages:
            rec["stages"].append("WRITEBACK")
            self.rf.write(instr["rd"], result)

        self.total_cycles += len(stages)
        self.instructions_executed += 1
        self.rf.pc = pc_next
        rec["branch_taken"] = branch_taken
        self.trace.append(rec)
        return True

    def run(self, max_steps=200):
        steps = 0
        while not self.halted and steps < max_steps:
            self.step()
            steps += 1

    @property
    def cpi(self):
        return self.total_cycles / self.instructions_executed if self.instructions_executed else 0


# --- হাতে-অ্যাসেম্বল করা প্রোগ্রাম: ১ থেকে ৫ পর্যন্ত যোগফল ---
program = [
    {"op": "ADDI",  "rd": 1, "rs1": 0, "imm": 0},        # 0: i = 0
    {"op": "ADDI",  "rd": 2, "rs1": 0, "imm": 0},        # 1: sum = 0
    {"op": "ADDI",  "rd": 3, "rs1": 0, "imm": 5},        # 2: limit = 5
    {"op": "ADDI",  "rd": 4, "rs1": 0, "imm": 1},        # 3: const_one = 1
    {"op": "ADD",   "rd": 1, "rs1": 1, "rs2": 4},        # 4: LOOP: i = i + 1
    {"op": "ADD",   "rd": 2, "rs1": 2, "rs2": 1},        # 5: sum = sum + i
    {"op": "BEQ",   "rs1": 1, "rs2": 3, "offset": 1},    # 6: i == limit -> PC 8
    {"op": "BEQ",   "rs1": 0, "rs2": 0, "offset": -4},   # 7: অ্যানকন্ডিশনাল জাম্প -> PC 4
    {"op": "STORE", "rs2": 2, "rs1": 0, "offset": 0},    # 8: mem[0] = sum
    {"op": "LOAD",  "rd": 5, "rs1": 0, "offset": 0},     # 9: r5 = mem[0]
    {"op": "HALT"},                                       # 10
]

cpu = SimpleCPU(program)
cpu.run()

print("=== এক্সিকিউশন ট্রেস ===")
for rec in cpu.trace:
    mem = f"  [ক্যাশ: {rec['mem_status']}]" if rec["mem_status"] else ""
    print(f"PC={rec['pc']:>2}  {rec['instr']['op']:<6}  {'>'.join(rec['stages']):<40}{mem}")

print()
print("চূড়ান্ত রেজিস্টার:", cpu.rf.regs)
print("r2 (sum)                       =", cpu.rf.read(2))
print("r5 (মেমরি থেকে রি-লোড করা sum)  =", cpu.rf.read(5))
print("ডেটা মেমরি:", cpu.dmem)
print()
print(f"ক্যাশ -- হিট: {cpu.cache.hits}, মিস: {cpu.cache.misses}")
print(f"মোট সাইকেল: {cpu.total_cycles}")
print(f"এক্সিকিউট হওয়া ইনস্ট্রাকশন: {cpu.instructions_executed}")
print(f"CPI = {cpu.total_cycles} / {cpu.instructions_executed} = {cpu.cpi:.4f}")

assert cpu.rf.read(2) == 15, "যোগফল ভুল!"
assert cpu.rf.read(5) == 15, "রি-লোড করা মান ভুল!"
assert cpu.cache.misses == 1 and cpu.cache.hits == 1, "ক্যাশ হিট/মিস প্রত্যাশিত মতো নয়!"
print()
print("সব যাচাই সফল -- ১+২+৩+৪+৫ = ১৫, সঠিকভাবে কম্পিউট হয়েছে।")